Low noise load pump for phase-locking loop

ABSTRACT

The invention concerns a load pump for phase-locking loop comprising a first current source ( 14 ), a second current source ( 16 ), several switches (M 1,  M 2,  M 3,  M 4 ) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means ( 18 ) adapted to store a physical quantity corresponding to the value of the current ( 11 ) supplied by the first current source ( 14 ), so that the value of the current ( 12 ) supplied by the second current source is substantially equal to the value of current ( 11 ) supplied by the first current source.

BACKGROUND OF THE INVENTION

The present invention relates to phase-locked loops, and in particularto the charge pumps used in some phase-locked loops.

1. Field of the Invention

FIG. 1 shows a conventional phase-locked loop, including a charge pump1. A reference frequency Fref coming from a quartz oscillator is appliedto a frequency divider 3. Frequency divider 3 is a divider by R and itprovides a signal Fdiv having a frequency equal to Fref/R. Signal Fdivis provided to a phase comparator 5. Phase comparator 5 also receives asignal Fcomp, the frequency of which corresponds to frequency Fvco ofthe output signal of the phase-locked loop, divided by a predeterminednumber N. Phase comparator 5 compares the phases of signals Fdiv andFcomp. Phase comparator 5 transmits a positive pulse on an output U ifsignal Fdiv is ahead of signal Fcomp, and a positive pulse on an outputD if signal Fcomp is ahead of signal Fdiv. The signals coming fromoutputs U and D of the phase comparator are provided to charge pump 1.Charge pump 1 drives a loop filter 7.

2. Discussion of the Related Art

Charge pump 1 includes a first current source 6A providing a current I1.Current source 6A is coupled to output OUT of the charge pump via aswitch Sa. Switch Sa is controlled by signal U provided by the phasecomparator. When signal U is high, switch Sa is on and current I1 isprovided by the charge pump to loop filter 7. The charge pump includes asecond current source 6B run through by a current I2. Current source 6Bis coupled to the charge pump output via a switch Sb. Switch Sb iscontrolled by signal D provided by phase comparator 5. When signal D ishigh, switch Sb is on and current I2 is absorbed by the charge pump fromloop filter 7.

Loop filter 7 outputs a control voltage Uc. Voltage Uc controls avoltage-controlled oscillator 9. Oscillator 9 provides a signal offrequency Fvco, at the output of the phase-locked loop. The output ofoscillator 9 drives a frequency divider 11. Frequency divider 11 dividesfrequency Fvco by N and provides signal Fcomp to phase comparator 5.

The operation of the phase-locked loop is the following.

To simplify, loop filter 7 will be considered to be only formed of acapacitor Cf connected between the charge pump output and the ground,control voltage Uc being the voltage across capacitor Cf. If the risingedge of signal Fdiv occurs before the rising edge of signal Fcomp,output U of the phase comparator switches high. Switch Sa then turns onand current I1 charges capacitor Cf of loop filter 7. The charge ofcapacitor Cf occurs during the on time Δt of switch Sa. In principle,duration Δt is equal to the time interval separating the rising edges ofsignals Fdiv and Fcomp. The charge stored by capacitor Cf thus increasesby I1.Δt, and control voltage Uc increases. Accordingly,voltage-controlled oscillator 9 provides a signal of higher frequencyFvco and the interval between the phases of signals Fdiv and Fcompdecreases. At equilibrium, signals Fdiv and Fcomp have a same phase. Thefrequency provided by voltage-controlled oscillator 9 then is at thedesired value Fvco=Fref.(N/R). Strictly speaking, the phases of signalFdiv and Fcomp are equal, plus the static phase deviation (it should bereminded that the static interval is the phase deviation exhibited bythe phase-locked loop when said loop is stabilized, this phase deviationgenerally causing no charge variation in loop filter 7). It is hereassumed that the static phase deviation is sufficiently low to beneglected.

Conversely, if the frequency provided by oscillator 9 is too high, therising edge of signal Fcomp occurs before the rising edge of signalFdiv. A positive pulse on terminal D then turns switch Sb on for a timeΔ′t, in principle equal to the time interval between the occurrence ofthe rising edges of signals Fcomp and Fdiv. Current I2 dischargescapacitor Cf, its amount of charge decreasing by I2.Δ′t. Voltage Ucdecreases and the output frequency of oscillator 9 decreases. Atequilibrium, the phase-locked loop is stabilized and the phases ofsignals Fdiv and Fcomp are the same.

The previously-described operation is defective in the case where thepulses on terminals U or D are very short. Indeed, the time necessary tooperate switches Sa or Sb may appear to be greater than the duration ofthe pulse generated by the phase comparator. In this case, switches Saor Sb do not have time to turn on and do not fulfil their function. Asolution to this problem consists of turning on controlled switch Sa orSb for a longer time, and of turning on, at the same time, the otherswitch, as illustrated in the diagrams of FIGS. 2a to 2 e.

FIGS. 2a to 2 e illustrate the case where frequency Fvco is smaller thanwhat is desired. In this case, the rising edge of signal Fdiv (FIG. 2a)occurs at a time t1 prior to time t2 at which occurs the rising edge ofsignal Fcomp (FIG. 2b). Signal U switches high at time t1, but, as canbe seen on the timing diagram illustrating signal U (FIG. 2c), signal Uremains high after time t2, and this until a time t3. During time t3−t2,signal D (FIG. 2d) also switches high, which turns on switch Sb. Induration t3−t2, loop filter 7 is run through by a current I1−I2 (FIG.2e) and capacitor Cf receives a small amount of electric charge equal to(I1−I2)×(t3−t2). Difference I1−I2, which is positive or negative, is aresidual intensity resulting from technological disparities having aneffect on current sources 6A and 6B. Duration t3−t2 is selected to besufficient for each of switches Sa and Sb to have time to turn on duringthis time. Thus, even when duration t2−t1 is very short, switches Sa orSb have in all cases time to turn on and the charge pump cansatisfactorily inject (respectively sample) current I1 (respectivelyI2).

At equilibrium, as shown in FIGS. 2a to 2 e after time t′0, signals Fdivand Fcomp are in phase. Their rising edges both appear at time t′1.Signals U and D both switch high at time t′1 and remain high until timet′3. Duration t′3−t′1 is equal to duration t3−t2. As can be seen in FIG.2e, at equilibrium, output current Iout of the charge pump is equal todifference I1−I2. This difference causes a misadjustment of thefrequency of oscillator 9 that the loop will attempt to compensate bygenerating a static phase shift, which results, in the power spectrum ofthe output signal of the phase-locked loop, in a undesirable noise inthe form of lines.

Further, the phase-locked loop exhibits a passband, determined by loopfilter 7. In this passband, the charge pump noise dominates, and it isdesirable to decrease it.

Further, charge pumps of prior art have a heavy consumption and take upa relatively large space.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a charge pump for aphase-locked loop such that the noise due to the pump is veryattenuated.

Another object of the present invention is to provide a charge pump inwhich errors due to technological dispersions are avoided.

Another object of the present invention is to provide a charge pumpenabling use of smaller components and enabling better integration.

Another object of the present invention is to provide a low-consumptioncharge pump.

To achieve these and other objects, the present invention provides acharge pump for a phase-locked loop including a first current source, asecond current source, several switches adapted to enablingcommunication of the first and/or the second current source with thecharge pump output. The second current source is controlled by a controlmeans adapted to storing a variable corresponding to the value of thecurrent provided by the first current source, so that the value of thecurrent provided by the second current source is substantially equal tothe value of the current provided by the first current source, thecontrol means comprising a first branch comprising a first storing meansand a second branch comprising a second storing means.

According to an embodiment of the present invention, the control meansstores said variable little before enabling communication of the firstand/or of the second current source with the charge pump output.

According to an embodiment of the present invention, the first currentsource is connected between a first supply voltage and a first node, andthe switches include:

a first switch connected between the first node and the charge pumpoutput, controlled by a first control signal,

a second switch connected between the first node and a second node,controlled by the inverse of the first control signal,

a third switch connected between the output of the charge pump and athird node, controlled by a second control signal,

a fourth switch connected between the second node and the third node,controlled by the inverse of the second control signal; and the secondcurrent source is connected between the third node and a second supplyvoltage.

According to an embodiment of the present invention, the first branchincludes a first capacitor coupled to the second node.

According to an embodiment of the present invention, the second branchincludes a fifth switch connected between the second node and the outputof the control means.

According to an embodiment of the present invention, the second branchincludes a second capacitor coupled to the second node via the fifthswitch.

According to an embodiment of the present invention, the second currentsource is formed by a first MOS-type transistor of a first conductivitytype.

According to an embodiment of the present invention, the first currentsource is formed by a second transistor, of a second conductivity type,and belongs to a current mirror, the current running through the firstcurrent source being equal to α times the value of a reference currentof the current mirror, with α greater than one.

According to an embodiment of the present invention, the first switch isformed of a third transistor of the second conductivity type, the secondswitch is formed of a fourth transistor of the second conductivity type,the third transistor is formed of a fifth transistor of the firstconductivity type, and the fourth transistor is formed of a sixthtransistor of the first conductivity type.

According to an embodiment of the present invention, the first supplyvoltage is a positive voltage, the second supply voltage is the groundvoltage, and the transistors of the first conductivity type areN-channel MOS transistors and the transistors of the second conductivitytype are P-channel MOS transistors.

The foregoing and other objects, features and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings, in which:

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a conventional phase-locked loop including a charge pump;

FIGS. 2a to 2 e show timing diagrams illustrating the operation of thephase-locked loop of FIG. 1 and

FIG. 2f shows a timing diagram illustrating the operation of a chargepump according to the present invention; and

FIG. 3 shows a specific embodiment of the present invention.

DETAILED DESCRIPTION

In FIG. 3, same references designate same elements as in FIGS. 1 and 2.

FIG. 3 shows an embodiment of a charge pump for a phase-locked loopaccording to the present invention. The charge pump is supplied by afirst supply voltage VDD and a second supply voltage VSS. In theembodiment shown, voltage VSS is the ground voltage (0 volt) and voltageVDD is a positive voltage with respect to the ground.

The charge pump includes a current source 14 arranged between supplyvoltage VDD and a node A of the charge pump. Current source 14 providesa charge current I1, intended for supplying a loop filter connected atthe output of the charge pump when a control signal U provided by aphase comparator located upstream of the charge pump is equal to 1.

In the shown embodiment, current source 14 includes a PMOS transistorMP1 having its source connected to voltage VDD and its drain connectedto node A. Transistor MP1 is run through by a current I1. The gate oftransistor MP1 is connected to the gate of a PMOS transistor MP2. Thesource of transistor MP2 is connected to voltage VDD. The drain oftransistor MP2 is connected to the gate of transistor MP2. TransistorMP2 is run through by a reference current Iref. Current source 14 isthus formed by means of a current mirror. Advantageously, referencecurrent Iref will not be chosen to be equal to I1, but the geometry oftransistors MP1 and MP2 will be chosen so that current I1 is equal toα.Iref, with α greater than 1. Thus, the consumption and the surface ofthe charge pump will be decreased.

A first pair of switches is connected to node A, each switch beingformed of a PMOS transistor, respectively M1 and M2. Transistor M1 hasits source connected to node A and its drain connected to output OUT ofthe charge pump. The gate of transistor M1 is controlled by a signal{overscore (U)}, corresponding to the inverse of signal U provided bythe phase comparator. When {overscore (U)} is equal to “0” (U=1),transistor M1 is on. Transistor M2 has its source connected to node Aand its drain connected to a node B of the charge pump. The gate oftransistor M2 is controlled by signal U coming from the phasecomparator. Transistor M2 is on when signal U is low (U=0). Inversesignals U and {overscore (U)} must partially overlap to ensure acontinuous conduction of current source 14.

A second pair of switches, formed of two transistors M3 and M4, isconnected to node B and to output OUT. Transistor M3 is an NMOStransistor, having its drain connected to output OUT and its source to anode C of the charge pump. The gate of transistor M3 is controlled byoutput D of the phase comparator. Transistor M3 is on when signal D ishigh (D=1). Transistor M4 is an NMOS transistor, having its drainconnected to node B and its source connected to node C. The gate oftransistor M4 is controlled by a signal {overscore (D)}, which is theinverse of signal D. Inverse signals D and {overscore (D)} mustpartially overlap to ensure a continuous conduction of current source14.

The state of transistors M1 to M4 according to the values of U and D canbe summed up in the two following tables:

Transistor U = 1 U = 0 M1 on off M2 off on Transistor D = 1 D = 0 M3 onoff M4 off on

A second current source 16 is arranged between node C and the secondsupply voltage VSS. Current source 16 is a controllable current source.Current I2 flowing therethrough is a function of a control signal UC2provided to a control terminal of source 16.

In the shown embodiment, source 16 is formed of an NMOS transistor MN1,having its drain connected to node C and its source connected to voltageVSS. The gate of transistor MN1 receives control signal UC2. In theshown embodiment, control signal UC2 is a voltage signal. Voltage UC2corresponds to the voltage between the gate and the source of transistorMN1. Transistor MN1 is run through by current I2. Since, in a MOStransistor in saturated state, the value of the drain current is, at thefirst order, biuniquely linked to the value of the gate-source voltage,discharge current I2 biuniquely depends on control voltage UC2.

The control terminal of current source 16 is driven by a control circuit18 providing voltage UC2. In the shown embodiment, circuit 18 includes afirst branch formed of a capacitor C1 connected between node B andsupply voltage VSS. Circuit 18 includes a second branch, also connectedbetween node B and supply voltage VSS, including a switch S connected inseries with a capacitor C2. Switch S is connected between node B and theoutput of circuit 18 providing voltage UC2. Capacitor C2 is connectedbetween the output of circuit 18 and second supply voltage VSS. Switch Sis controlled by a signal AZ. Switch S is off (node B isolated form theoutput of circuit 18) when signal AZ is equal to 1. Switch S is on (nodeB in communication with the output of circuit 18) when signal AZ isequal to 0.

To explain the operation of the charge pump according to the presentinvention, reference will be made to the timing diagrams of FIG. 2, inwhich, in addition to the signals used to explain the operation of thecharge pump of prior art, signal AZ is shown (FIG. 2f).

In a first phase, reaching time t0, U=D=0. Signal AZ is also equal to 0.The only on transistors of the pairs of switches are transistors M2 andM4. Switch S is on and node B communicates with the output of circuit18. Transistors M1 and M3 being off, no current transits through outputOUT. Current I1 reaching node A runs through transistor M2 and reachesnode B. First, a portion of current I1 is used to charge capacitor C1and, via on switch S, capacitor C2. The portion of current I1 which hasnot been used to charge capacitors C1 and C2 crosses transistor M4 andtransistor MN1. At equilibrium, capacitors C1 and C2 are charged andabsorb no current. Accordingly, current I1 provided by current source 14entirely crosses current source 16 and, thereby, current source 16 isrun through by a current I2 strictly equal to current I1. This lastpoint is particularly important. Indeed, in prior art, even if it wastried to have identical current sources 6A and 6B, technologicaldispersions would result in that, as seen, current I1 is never strictlyequal to I2.

At time t0, little before occurrence of the rising edge of signal Fdivat time t1 (it should be reminded that FIG. 2 shows the case wheresignal Fdiv is ahead of signal Fcomp, but the reasoning is similar andcan be readily deduced in the case where signal Fcomp is ahead of signalFdiv), signal AZ switches to “1” and switch S turns off. The turning-offof switch S isolates capacitor C2 of node B. Capacitor C2 exhibitsacross its terminals a voltage UC2, which will remain constant since thegate of transistor MN1 absorbs no current. Since voltage UC2 remainsconstant, current I2 crossing current source 16 will remain constant andstrictly equal to the value of current I1 at time t0. Circuit 18 thusacts as a means for storing the value of current I1 before turning-on ofone of transistors M1 and M3. Preferably, time t0 will be chosen to beas close as possible to time t1, for the storage of current I1 to beperformed on a value of I1 as close as possible to the time when thecharge pump communicates with the loop filter. It should be remindedthat, although current I1 is, in principle, a constant current, currentI1 is altered by noise. Current I1 is thus submitted to variations whichmay certainly be small, but introduce noise at the output of thephase-locked loop when the charge pump communicates with the loopfilter.

It should here be noted that capacitor C2 can be omitted. Indeed, thevalue of this capacitor is small, typically on the order of 5picofarads. If transistor MN1 is formed so that its gate-source straycapacitance is sufficient, for example by means of a transistor ofsufficient dimensions, the stray capacitance of transistor MN1 may beused as a capacitor C and said capacitor may be suppressed.

At time t1, signal U switches to “1”. This results in turning ontransistor M1 and turning off transistor M2. Current I1 reaching node Ais then directed towards output OUT and injected into the loop filter todecrease the phase deviation between signals Fdiv and Fcomp. Betweentimes t1 and t2, signal D remains equal to “0”. Transistor M3 thusremains off, and transistor M4 remains on. Current I2 running throughcurrent source 16 is provided by capacitor C1, which discharges atconstant current through transistors M4 and MN1. The value of voltageUC2 does not substantially vary between times t1 and t2, and current I2,between times t1 and t2, remains equal to the value of current I1 attime t0. The capacitance of capacitor C1 is chosen to be sufficientlylarge to be able to provide current I2 for a sufficient durationcorresponding to the phase deviation between Fdiv and Fcomp. A typicalvalue of the capacitance of capacitor C1 is approximately 30 picofarads.

At time t2, signal D switches to “1”, signals U and AZ remaining at “1”.Then, transistor M3 turns on and transistor M4 turns off. Current source16 then is in connection with output OUT, and the current transitingthrough output OUT is equal to current I1 provided by source 14 at timet2 decreased by current I2 equal, as it should be reminded, to currentI1 provided by source 14 at time t0. Since the time interval between t2and t0 is small, the value of current I1 has varied little between thesetwo times. Thereby, it can be considered that the source of I1 isaltered by a noise that can be decomposed in a low-frequency noise and ahigh-frequency noise. Between times t0 and t2, only the high-frequencynoise of current I1 has varied. The low-frequency noise having beenmemorized at time to by current I2, the current provided at output OUTis devoid of the low-frequency noise altering source I1, which is aconsiderable advantage with respect to prior art. The closest time t0 isto time t1, the better the noise elimination and the smaller theresidual current transiting through output OUT. Thus, it will beadvantageous to have switch S turn off as close as possible to time t1.

At time t3, signals U and D both switch to “0”, signal AZ remaining at“1”. In this case, transistors M1 and M3 turn off and transistors M2 andM4 turn on. Current I1 reaching A is directed to node B. Capacitance C1having discharged during step t1−t2, to return to equilibrium, a portionof current I1 will be used to recharge it.

At time t4, signal AZ switches to “1” and switch S turns on. Thissituation is similar to that preceding time t0, signals U, D, and AZ allbeing equal to “0”. When equilibrium is reached, capacitors C1 and C2are charged, and current I2 is strictly equal to current I1. Time t4 ischosen so that the switches of the first and second pair of switcheshave had time to switch. Time t4 can be chosen within a relatively largetime range.

When the loop is stabilized (after time t′0), only the high-frequencynoise altering current sources 14 and 16 is transmitted during timet′3−t′1.

Thus, in the present invention, circuit 18 is a control circuit ofcurrent source 16, which ensures that current I2 running through currentsource 16 follows the variations of current I1 running through currentsource 14. Before the charge pump provides current on its output OUT,means 18 memorizes the value of current I1 and, when both currentsources 14 and 16 communicate with output OUT, the value of current I2provided by current source 16 is equal to the stored value of currentI1. As compared to prior art, this enables, on the one hand, reducingthe residual current I1−I2 provided at the charge pump output when eachof these sources communicates with the loop filter, and on the otherhand suppressing the low-frequency noise in the current provided by thecharge pump.

Another advantage of the charge pump according to the present inventionis that it is easily integrable. It can use smaller transistors andconsumes less than in prior art. To have a good matching on the currentmirrors and to have a small low-frequency noise, large transistors mustconventionally be provided. Since, according to the present invention, amemorization is performed, which suppresses the low-frequency noise andinterval I1−I2, transistors MP1, MP2, and MN1 smaller than in prior artcan be used. Further, conventionally, to decrease the low-frequencynoise in the loop, the current of sources I1 and I2 is increased (thenoise of a MOS transistor increases as {square root over (I)} but thegain of this noise towards the output is a 1/I function). Since thelow-frequency noise is suppressed, the value of the current can bedecreased. Factor Iref-I1 also is a reason of the consumption decrease.

Of course, the present invention is likely to have various alterations,modifications, and improvements which will readily occur to thoseskilled in the art.

The case where voltage VDD is a positive supply voltage and voltage VSSis a supply voltage equal to 0 (ground voltage) has been described. Ofcourse, voltage VSS may be different, for example, negative with respectto the circuit ground. Also, the polarities of voltages VDD and VSS maybe inverted. In this case, the N-type transistors will be replaced withP-type transistors, and vice-versa.

Also, the MOS transistors of the described embodiment may, if desired,be replaced with bipolar transistors, but, in this case, current source16 will have to be formed so that it only takes a negligible currentfrom its control terminal, so that the voltage on its control terminal,if current source 16 is voltage-controlled, remains at a constant value.

Finally, switch S has not been specifically described. Of course, it maybe any appropriate switch device, for example, a MOS transistor,appropriately connected and controlled.

Having thus described at least one illustrative embodiment at theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended to be limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

What is claimed is:
 1. A charge pump for a phase-locked loop including afirst current source, a second current source, several switches adaptedto enabling communication of the first and/or the second current sourcewith the charge pump output, wherein the second current source iscontrolled by a control means adapted to storing a variablecorresponding to the value of the current provided by the first currentsource, so that the value of the current provided by the second currentsource is substantially equal to the value of the current provided bythe first current source, the control means comprising a first branchcomprising a first storing means and a second branch comprising a secondstoring means, wherein the first current source is connected between afirst supply voltage and a first node, and wherein the switches include:a first switch connected between the first node and the charge pumpoutput, controlled by a first control signal, a second switch connectedbetween the first node and a second node, controlled by the inverse ofthe first control signal, a third switch connected between the output ofthe charge pump and a third node, controlled by a second control signal,a fourth switch connected between the second node and the third node,controlled by the inverse of the second control signal, and wherein thesecond current source is connected between the third node and a secondsupply voltage.
 2. The charge pump of claim 1, wherein the first switchis formed of a third transistor of the second conductivity type, thesecond switch is formed of a fourth transistor of the secondconductivity type, the third transistor is formed of a fifth transistorof the first conductivity type, and the fourth transistor is formed of asixth transistor of the first conductivity type.
 3. The charge pump ofclaim 1, wherein the first supply voltage is a positive voltage, thesecond supply voltage is the ground voltage, and the transistors of thefirst conductivity type are N-channel MOS transistors and thetransistors of the second conductivity type are P-channel MOStransistors.
 4. The charge pump of claim 1, wherein the first branchincludes a first capacitor coupled to the second node.
 5. The chargepump of claim 1, wherein the second branch includes a fifth switchconnected between the second node and the output of the control means.6. The charge pump of claim 5, wherein the second branch includes asecond capacitor coupled to the second node via the fifth switch.
 7. Acharge pump for a phase-locked loop including a first current source, asecond current source, several switches adapted to enablingcommunication of the first and/or the second current source with thecharge pump output, wherein the second current source is controlled by acontrol means adapted to storing a variable corresponding to the valueof the current provided by the first current source, so that the valueof the current provided by the second current source is substantiallyequal to the value of the current provided by the first current source,the control means comprising a first branch comprising a first storingmeans and a second branch comprising a second storing means, wherein thesecond branch includes a fifth switch connected to the output of thecontrol means.
 8. The charge pump of claim 7, wherein the second branchincludes a second capacitor coupled to the fifth switch.